PSD511B1 datasheet(97/153 Pages) STMICROELECTRONICS

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PSD5XX Family

Counter/Timer

(Cont.)

9.6.2.12 Sample Counter/Timer0 Initialization In PULSE Mode

Following is a sample initialization routine for Counter/Timer0 to operate in PULSE mode.

The assembly language commands do not correspond to any particular microcontroller.

Configure CSIOP for Microcontroller access to Counter/Timer registers and I/O ports for

initialization of Counter/Timers. For the values of each register, refer to Tables 30 and 31.

Use PSDsoft supplied by WSI to configure the portion related to Counter/Timers. Also refer

to the Section on the PSD5XX I/O Ports.

Clear All Counter/Timers

LOAD CNTR0, 0000h

; Clear Counter/Timer 0

LOAD CNTR1, 0000h

; Clear Counter/Timer 1

LOAD CNTR2, 0000h

; Clear Counter/Timer 2

LOAD CNTR3, 0000h

; Clear Counter/Timer 3

Scaling of Clock (common to all Counter/Timers)

LOAD DLCY, 02h

;Delay Cycles(DLCY) = 2, k value is selected in

;Global Register by setting Scale-Bit

Counter/Timer 0 Initialization (Command Register0 CMD0)

LOAD CMD0, 6Fh

;Pulse mode (D0 = 1)

;Increment (D1 = 1)

;Select Counter/Timer (D2 = 1)

;Output Pulse Active High (D3 = 1)

;Load Signal on Input pin High going transition (D4 = 0)

;Input control from PIN (not PPLD macrocell) (D5 = 1)

;Load&Store control activated by Pin (D6 = 0)

;Enable count (D7 = 1)

LOAD IMG0,FFF7h

;Load Counter/Timer0 Image Register with count (pulse width)

;needed (pulse duration of 8 timer clock cycles)

LOAD Special Reg A,1

;Configure PA0 as A timer = 0 output by writing a “1” to Port A

;Special Function Register

Global Register Configuration

LOAD Global, 03h

;Non WatchDog mode

;Pulse mode

;All CTUs enabled

;Scale-Bit = 1

;Input clock is divided by 6

Now if Pin PE3 on port E is input with a high going signal:

t This signal causes Counter/Timer0 to get a value (FFF7h) loaded from its

associated image register (IMG0) and causes the Counter/Timer0 to start counting

from FFF7h (increment) until it overflows and issues a Terminal Count0 (TC0).

t During counting Port A pin (PA0) outputs a high going one-shot pulse with a width

equal to (Max count possible – initial count value loaded, i.e. 8 timer clock cycles

in this example).

t If the interrupt controller is configured to receive TC0, it will cause the interrupt

INT0 to occur.

PSD511B1 Datasheet(PDF) 97 Page - STMicroelectronics

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