PSD511B1 datasheet(98/153 Pages) STMICROELECTRONICS

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PSD5XX Family

General Description

The PSD5XX includes logic for sensing, masking, priority decoding and identifying up to

eight internal interrupts. The PSD5XX interrupt controller can generate interrupts from two

dedicated PPLD product terms, two PPLD Macrocell outputs and four terminal-count

outputs of the Counter/Timer unit.

The four interrupts generated by the PPLD can be user defined using the WSI PSDsoft

Windows compatible PC based software. Figure 45 details the basic building blocks

of the PSD5XX Interrupt Controller and Figure 46 shows its interface with other sections of

the PSD5XX.

Features

The PSD5XX interrupt controller has the following features:

t Can accept eight interrupt inputs

t PPLD product terms, PPLD Macrocell outputs and Terminal Counts (TCs) of

Counter/Timers can cause interrupts.

t Interrupts generated from the PPLD canbe user defined.

t All interrupt inputs are priority decoded, IR7 has highest priority and IR0 the

lowest priority.

t Each interrupt can be configured as either EDGE or LEVEL sensitive using the

EDGE/LEVEL register.

t Each interrupt can be individually masked using a mask register.

t At RESET all interrupts are MASKED.

t Interrupt Request Latch provides the status of all interrupts.

t Reading an Interrupt vector location clears the corresponding pending interrupt.

t Any of these interrupts trigger a GLOBAL interrupt output available as an output at port

E (PE2) and/or as an input to the PPLD.

9.7.1 Interrupt Operation

On RESET all Registers and Latches are cleared and all interrupts are masked. During

initialization of the interrupt controller, relevant interrupts are un-masked and defined

whether EDGE or LEVEL sensitive. When one or more interrupts are raised high,

the “interrupt request latch” latches in all the non-masked interrupts. A 3-bit priority encoder

assigns the priority to the non-masked pending interrupts. The MCU (microcontroller)

can clear the Edge-sensitive pending interrupts by reading the “Interrupt Read Clear

“Interrupt Read Clear Register”. The MCU would typically service each interrupt in

sequence according to priority. Refer to Table 28 regarding priorities of various interrupts.

Any of these interrupts trigger a GLOBAL interrupt output available as an input to the PPLD

(INTR2PLD) and as output at port E (PE2). Refer to Figures 45 and 46 for details of the

interrupt architecture.

Interrupt

Priority

IR 7

HIGHEST

IR 6

IR 5

IR 4

IR 3

IR 2

IR 1

IR 0

LOWEST

Table 28. Interrupt Priority Table

9.7

Interrupt

Controller

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