PSD511B1 datasheet(102/153 Pages) STMICROELECTRONICS

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PSD5XX Family

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sense7

Sense6

Sense5

Sense4

Sense3

Sense2

Sense1

Sense0

Interrupt Operation (cont.)

Interrupt Edge/Level Select Register

Bits sense 0

... sense 7 correspond to interrupt 0 ... interrupt 7.

When these bits are set to

1 = LEVEL sensitive

0 = EDGE sensitive (positive edge)

At RESET these bits initialize as 0 i.e., all interrupts come up as Edge sensitive.

Interrupt Read Clear Register

This is a read only register. Reading this register during initialization clears all the pending

edge sensitive interrupts.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ir 7

ir 6

ir 5

ir 4

ir 3

ir 2

ir 1

ir 0

Interrupt Request Latch Register

Bits ir 0...ir 7 correspond to interrupt 0 ... interrupt 7.

When any of these bits are set by the interrupt controller to a “1”, the corresponding

Interrupt is pending service.

The MCU can read the interrupt request latch which shows the status of all interrupts. The

entire interrupt request latch can be cleared by reading the Interrupt Read Clear Register,

but Level sensitive interrupts cannot be cleared.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

***

vect 2

vect 1

vect 0

NOTE: * = Reserved for future use, bits set to zero.

Interrupt Priority Status Register

The value of these 3 bits (vect2, vect1 and vect0) indicates the highest priority of the

interrupt to be serviced among multiple interrupts pending. Refer to the table above for

priorities of various interrupts. Reading this register clears the highest pending interrupt.

Interrupt

Controller

(Cont.)

PSD511B1 Datasheet(PDF) 102 Page - STMicroelectronics

PSD511B1 Datasheet(HTML) 102 Page - STMicroelectronics

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