PSD511B1 datasheet(103/153 Pages) STMICROELECTRONICS

103 / 153 page

PSD5XX Family

100

Interrupt

Controller

(Cont.)

Interrupt Operation (Cont.)

9.7.2 Input/Output

Interrupt inputs INT4 and INT5 originate from two dedicated PPLD product terms PT2INT4

and PT2INT5. Interrupt inputs INT6 and INT7 originate from the outputs of the PPLD

Macrocells MC2INT6 and MC2INT7 as described in the next section and the remaining

interrupt inputs INT0 through INT3 originate from four Terminal-Count (TC) outputs of the

Counter/Timers. If an External event has to cause an interrupt in the PSD5XX, it has to be

routed through the PPLD.

Regarding output from the Interrupt Controller, whenever an unmasked interrupt occurs, a

Global Interrupt signal is generated. The Global Interrupt signal can be used as a ZPLD

input (INTR2PLD). Refer to Figure 45 for details. It can also be driven off the chip by using

the special-function out capability of Port E (PE2) as INTR_OUT. In either case, the Global

Interrupt indicates to the MCU that an internal PSD5XX interrupt has occurred. Refer to the

section on I/O ports for specific details of setting up the port functions.

9.7.3 PPLD Macrocell

Interrupt inputs INT6 and INT7 originate two dedicated PPLD Macrocells. Each of these

PPLD Macrocells have two product terms as inputs that are inputted into a PPLD Macrocell

as shown in Figure 47. The outputs of both PPLD Macrocells MC2INT6 and MC2INT7 are

either Combinatorial or Register mode. The polarity of the product terms is programmable.

Refer to the section on “ZPLD” for further reference on the PPLD.

9.7.4 Interrupt Flowchart

The flowchart in Figure 48 explains the overall initialization and the servicing

of the interrupts.

PSD511B1 Datasheet(PDF) 103 Page - STMicroelectronics