PSD511B1 datasheet(81/153 Pages) STMICROELECTRONICS

81 / 153 page

PSD5XX Family

Counter/Timer

Operation

(Cont.)

9.6.1.8 Counter/Timer Clock Input

All Counter/Timers 0 through 3 have a common clock source. The Counter/Timers are

clocked from the output of a highly flexible and high resolution Divisor unit. The Divisor’s

input is the external Clock input pin. The Divisor DIV is a number in the range of

<= DIV <= 280. Refer to Table 22 for exact values of DIV for different clock values.

Figure 42 details the PSD5XX Counter clock generation.

The Counter/Timer CLOCK input

(External Clock input)

(DIV)

where DIV = N * K and N = (4 + DLCY).

The value of K depends on the Scale-Bit (Bit 0 in the Global Command Register) in the

“Global Command Register” , K = 8 when Scale-Bit is set to 1 and K = 1 when Scale-Bit is

set to 0. DLCY is the number of Delay Cycles in the range of 0

<= DLCY <= 31 set up in the

Delay Cycle Register. The fastest clock to service the Counter/Timer is = (Clock input / 4).

The maximum External Clock input value is 28 MHz and the fastest internal count frequency

is 7.0 MHz, i.e., a resolution of 143 ns. (Higher resolution can be achieved by using in

conjunction with GPLD macrocells). The default value of DIV is 4 (following a reset both K

and DLCY contain zeroes).

9.6.1.7 Terminal Counts (TCs)

The terminal counts (TC0 – TC3) generated by the Counter/Timers are made available

at Port E as outputs or as feedbacks to the ZPLD. Refer to Table 27a for pin assignments.

The terminal counts can be used to concatenate the 16-bit Counter/Timers into a

larger counter. Only the trailing edge of the TC signal can be used as input to another

Counter/Timer. For example, concatenating CTU0 and CTU1 requires the following

PPLD equation in the PSDabel file:

mc2t mr1 = tc0;

In order for a TC signal to come out, its respective bit in the Port E Special Function Out

A TC signal goes high for the duration of at least four CLKIN periods whenever its

corresponding Timer Counting-Register overflows or underflows.

Figure 41 gives the timing relationship between CLKIN and the TC signal.

Figure 41. Timing Relationship Between CLKIN and the TC Signal.

4 CLKIN PERIODS

CLKIN

TC - SIGNAL

30ns

NOTES: 1. Overflow occurs when a counter value changes from FFFFh to 0000h during incrementing.

2. Underflow occurs when a counter value changes from 0000h to FFFFh during decrementing.

PSD511B1 Datasheet(PDF) 81 Page - STMicroelectronics

PSD511B1 Datasheet(HTML) 81 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL