PSD511B1 datasheet(86/153 Pages) STMICROELECTRONICS

86 / 153 page

PSD5XX Family

9.6.2.1 Global Command Register

This is used to specify the operation mode of the Counter/Timer and to start or stop the

Counter/Timer. Therefore during the initialization of the Counter/Timer registers, the Global

Command Register should always be configured last.

Counter/Timer

Registers

(Cont.)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

***

Watch

Global

Counter

Scale

Dog

Mode

Start

NOTE: * = Not used.

At RESET all bits come up as 0’s.

Watch Dog Bit:

When this bit is

0: Watch Dog mode is NOT selected.

1: Watch Dog Counter/Timer (Counter 2) is active. This bit can be

turned off by RESET only.

NOTE: Whenever this bit is set to 1, the COUNTER START bit should

also be set to 1. Otherwise the Counter/Timer will always be off,

i.e., once this bit is set, access to Counter 2 Registers and the Global

Command Registers are blocked.

Global Mode Bit:

When this bit is set to a

0: All Timers/Counters are set to Waveform or Pulse Mode.

1: All Timers/Counters are set to operate in Event Counter or Time

Capture Mode.

NOTE: Further selection of modes is done in individual CMD registers.

Counter Start Bit: When this bit is set to

0: ALL CTUs are disabled and can be re-initialized.

1: ALL CTUs are enabled.

Scale Bit:

When this bit is set to

0: The clock to all Counter/Timers is divided by 1.

1: The clock to all Counter/Timers is divided by 8.

PSD511B1 Datasheet(PDF) 86 Page - STMicroelectronics

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