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PSD511B1 Datasheet(PDF) 84 Page - STMicroelectronics |
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PSD511B1 Datasheet(HTML) 84 Page - STMicroelectronics |
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84 / 153 page  PSD5XX Family 81 Address Register Name Address Register Name Offset Offset +A9h STATUS FLAGS +A8h GLOBAL COMMAND +A6h DLCY +A5h SOFTWARE LOAD/STORE +A4h FREEZE COMMAND +A3h CMD3 +A2h CMD2 +A1h CMD1 +A0h CMD0 +9Fh CNTR3 +9Eh CNTR3 +9Dh CNTR2 +9Ch CNTR2 +9Bh CNTR1 +9Ah CNTR1 +99h CNTR0 +98h CNTR0 +97h IMG3 +96h IMG3 +95h IMG2 +94h IMG2 +93h IMG1 +92h IMG1 +91h IMG0 +90h IMG0 Table 23. Offset Address Map of Counter/Timer-Unit Registers Counter/Timer Operation (Cont.) 9.6.2 Counter/Timer Registers Registers CNTR0,CNTR1,CNTR2 and CNTR3 serve as actual counting logic. Registers IMG0,IMG1,IMG2 and IMG3 serve as images of these Counter/Timers. Depending upon the selected mode of operation, a Counter can load a new value or transfer its content to the image register. Registers IMG0 - IMG3 and CNTR0 - CNTR3 are accessible to the Microcontroller only before setting the start bit (Bit 1 in the Global Command Register). When CNTR0-CNTR3 are active, the value in the read operation is not guaranteed to be stable and during a write operation there could be contention between the image register write and microcontroller write. Therefore the access of registers CNTR0-CNTR3 should be suspended when the Counter/Timers are active. Only IMG0, IMG1, IMG2 and IMG3 registers are accessible when the Counter/Timers are active. Tables 23 and 23a give the address map for the various port and Counter/Timer-unit registers. This address offset map is of the host processor, relative to CSIOP (Chip Select Input Output Port) i.e. address space allocated by the host Microcontroller to access all the PSD5XX embedded peripherals. Table 23a is for 16-bit Motorola Microcontrollers which require different address offsets. |
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