PSD511B1 datasheet(37/153 Pages) STMICROELECTRONICS

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PSD5XX Family

9.2.5 Optional Features

The PSD5XX provides two optional features to add flexibility to the Bus Interface:

1. Address In

Port A can be configured as high order address (A16-A23) inputs to the ZPLD for

EPROM or other decoding. Inputs are latched by ALE/AS if Multiplexed Bus is selected.

Other ports can be configured as address input ports for the ZPLD. These inputs should

not be used for EPROM decoding and are not latched internally.

2. Address Out

For multiplexed bus only. Latched address lines A0-A15 are available on

Port A, B, C, D, or E.

Details on the optional features are described in the I/O Port section.

Bus

Interface

(Cont.)

9.2.6 Bus Interface Examples

The next four figures show the PSD5XX interfacing with some popular microcontrollers.

The examples show only the basic bus connections; some of the pin names on the

PSD5XX parts change to reflect the actual pin functions.

Figure 17 shows an interface to the 80C31. The 80C31 has a 16 bit address bus and an

8-bit data bus. The lower address byte is multiplexed with the data bus. The RD and WR

signals are used for accessing the data memory (SRAM) and the PSEN signal is for reading

program memory (EPROM). The ALE signal is active high and is used to latch the address

internally. Port C provides latched address outputs A[7:0]. Ports A, B, D, and E (PE2-PE7)

can be configured to perform other functions. The RSTOUT reset to the 80C31 is generated

by the ZPLD from the RESET input. This configuration eliminates any reset race condition

between the 80C31 and the PSD5XX.

Figure 18 shows the 68HC11 interface, which is similar to the 80C31 except the PSD5XX

generates internal RD and WR from the 68HC11’s E and R/W signals.

In Figure 19, the Intel 80C196 microcontroller is interfaced to the PSD5XX. The 80C196

has a multiplexed 16-bit address and data bus. The BHE signal is used for data byte

selection. Ports C and D are used as output ports for latched address A[15:0]. Pins PE6

and PE7 can be programmed as ZPLD outputs to provide the READY and BUSWIDTH

control signals to the 80C196.

Figure 20 shows Motorola’s MC68331 interfacing to the PSD5XX. The MC68331 has a

16-bit data bus and a 24-bit address bus. D15-D8 from the MC68331 are connected to

Port D, and D7 – D0 are connected to Port C.

PSD511B1 Datasheet(PDF) 37 Page - STMicroelectronics