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ST7265X Datasheet(PDF) 65 Page - STMicroelectronics |
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ST7265X Datasheet(HTML) 65 Page - STMicroelectronics |
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65 / 166 page ![]() ST7265x 65/166 11.3 USB INTERFACE (USB) 11.3.1 Introduction The USB Interface implements a full-speed func- tion interface between the USB and the ST7 mi- crocontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and USB Data Buffer interface. No external com- ponents are needed apart from the external pull- up on USBDP for full speed recognition by the USB host. 11.3.2 Main Features s USB Specification Version 2.0 Compliant s Supports Full-Speed USB Protocol s Five Endpoints (including default endpoint) s CRC generation/checking, NRZI encoding/ decoding and bit-stuffing s USB Suspend/Resume operations s Special Data transfer mode with USB Data Buffer Memory (2 x 512 bytes for upload or download) to DTC s On-Chip 3.3V Regulator s On-Chip USB Transceiver 11.3.3 Functional Description The block diagram in Figure 40, gives an overview of the USB interface hardware. For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org. Serial Interface Engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmis- sion/reception, and handshaking as required by the USB standard. It also performs frame format- ting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. Data Transfer to/from USB Data Buffer Memory When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place to/from the USB data buffer. In normal con- figuration (MOD[1:0] bits=00 in the CTLR register), at the end of the transaction, an interrupt is gener- ated. Interrupts By reading the Interrupt Status register, applica- tion software can know which USB event has oc- curred. Figure 40. USB Block Diagram CPU Transceiver 3.3V Voltage Regulator SIE ENDPOINT BUFFER USB Address, and interrupts USBDM USBDP USBVCC 48 MHz REGISTERS REGISTERS data busses USBGND BUFFER USB DATA INTERFACE 1 |
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