ST7265X datasheet(77/166 Pages) STMICROELECTRONICS

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ST7265x

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USB INTERFACE (Cont’d)

Download Mode

IN transactions are managed the same way as in

normal mode (by software with the help of CTR in-

terrupt) but OUT transactions are managed by

hardware. This means that no CTR interrupt is

generated at the end of an OUT transaction and

the STAT_RX bits are set to valid by hardware

when the buffer is ready to receive new data. This

allows the 512-byte buffer to be written without

software intervention.

If the USB interface receives a packet which has a

length lower than the maximum packet size (writ-

ten in the CNT2RXR register, see Note below), the

USB interface switches back to normal mode and

generates a CTR interrupt and the STAT_RX bits

of the EP2R register are set to NAK by hardware

as in normal mode.

Upload Mode

OUT transactions are managed in the same way

as normal mode and IN transactions are managed

by hardware in the same way as OUT transactions

in download mode.

Bits 5:4 Reserved, forced by hardware to 0.

Bit 3 = CTR_RX

Reception Correct Transfer.

This bit is set by hardware when a correct transfer

operation is performed in reception. This bit must

be cleared after that the corresponding interrupt

has been serviced.

Bit 2 = DTOG_RX

Data Toggle, for reception

transfers.

It contains the expected value of the toggle bit

(0=DATA0, 1=DATA1) for the next data packet.

USB INTERFACE (Cont’d)

The receiver toggles DTOG_RX only if it receives

a correct data packet and the packet’s data PID

matches the receiver sequence bit.

Bits 1:0 = STAT_RX [1:0]

Status bits, for reception

transfers.

These bits contain the information about the end-

point status, which is listed below:

Table 24. Reception Status Encoding

These bits are written by software, but hardware

sets the STAT_RX bits to NAK when a correct

transfer has occurred (CTR=1) addressed to this

endpoint, so the software has the time to examine

the received data before acknowledging a new

transaction.

Note: These bits are write protected in download

mode (if MOD[1:0] =10b in the EP2RXR register)

ENDPOINT

TRANSMISSION

(EP2TXR)

Read/Write

Reset value: 0000 0000 (00h)

This register is used for controlling Endpoint 2

transmission. Bits 2:0 are also reset by a USB re-

set, either received from the USB or forced

through the FRES bit in the CTLR register.

Bit 3 = CTR_TX

Transmission Transfer Correct.

This bit is set by hardware when a correct transfer

operation is performed in transmission. This bit

must be cleared after the corresponding interrupt

has been serviced.

0: No CTR in transmission on Endpoint 2

1: Correct transfer in transmission on Endpoint 2

STAT_RX1 STAT_RX0

Meaning

DISABLED: reception trans-

fers cannot be executed.

STALL: the endpoint is stalled

and all reception requests re-

sult in a STALL handshake.

NAK: the endpoint is naked

and all reception requests re-

sult in a NAK handshake.

VALID: this endpoint is ena-

bled for reception.

0000

CTR_T

DTOG

_TX

STAT_

TX1

STAT_

TX0

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