ST7265X datasheet(30/166 Pages) STMICROELECTRONICS

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ST7265x

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RESET SEQUENCE MANAGER (Cont’d)

6.2.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

electrical characteristics section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in

order to be recognized. This detection is asynchro-

nous and therefore the MCU can enter reset state

even in HALT mode.

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 18), the

signal on the RESET pin will be stretched. Other-

wise the delay will not be applied (see long ext.

Reset in Figure 18).

Starting from the external RESET pulse recogni-

tion, the device RESET pin acts as an output that

is pulled low during at least tw(RSTL)out.

6.2.3 Internal Low Voltage Detection RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

Power-On RESET

Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 18.

The LVD filters spikes on VDD shorter than tg(VDD)

to avoid parasitic resets.

6.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 18.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 19. Reset Block Diagram

fCPU

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

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