ST7265X datasheet(59/166 Pages) STMICROELECTRONICS

59 / 166 page

ST7265x

59/166

WATCHDOG TIMER (Cont’d)

11.1.4 Software Watchdog Option

If Software Watchdog is selected by option byte,

the watchdog is disabled following a reset. Once

activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

11.1.5 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the CR is not used.

11.1.6 Low Power Modes

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as Input before executing the HALT instruction.

The main reason for this is that the I/O may be

wrongly configured due to external interference

or by an unforeseen logical condition.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the I bits in the

CC register to allow interrupts, the user may

choose to clear all pending interrupt bits before

executing the HALT instruction. This avoids en-

tering other peripheral interrupt routines after ex-

ecuting the external interrupt routine

corresponding to the wake-up event (reset or ex-

ternal interrupt).

11.1.7 Interrupts

None.

Mode

Description

WAIT

No effect on Watchdog.

HALT

If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog

is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to

generate a reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case

of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state).

Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode

ST7265X Datasheet(PDF) 59 Page - STMicroelectronics

ST7265X Datasheet(HTML) 59 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL