ST7265X datasheet(54/166 Pages) STMICROELECTRONICS

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ST7265x

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I/O PORTS (Cont’d)

9.4 Register Description

DATA REGISTER (DR)

Port x Data Register

PxDR with x = A, B, C, D, E or F.

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken into account

even if the pin is configured as an input; this allows

to always have the expected level on the pin when

toggling to output mode. Reading the DR register

always returns the digital value applied to the I/O

pin (pin configured as input).

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register

PxDDR with x = A, B, C, D, E or F.

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

OPTION REGISTER (OR)

Port x Option Register

PxOR with x = A, C, D, or E

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implement-

ed. In this case the DDR register is enough to se-

lect the I/O pin configuration.

The OR register allows to distinguish: in input

mode if the interrupt capability or the basic config-

uration is selected, in output mode if the push-pull

or open drain configuration is selected.

Each bit is set and cleared by software.

Input mode:

0: Floating input

1: Floating input with interrupt (ports A, C and D).

For port E configuration, refer to Table 14.

Output mode:

0: Output open drain (with P-Buffer deactivated)

1: Output push-pull

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

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