ST7265X datasheet(80/166 Pages) STMICROELECTRONICS

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ST7265x

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11.4 16-BIT TIMER

11.4.1 Introduction

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

11.4.2 Main Features

Programmable prescaler: f

CPU divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

2 alternate functions on I/O ports (OCMP1,

OCMP2)

The Block Diagram is shown in Figure 45.

11.4.3 Functional Description

11.4.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er).

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 27 Clock

Control Bits. The value in the counter register re-

peats every 131.072, 262.144 or 524.288 CPU

clock cycles depending on the CC[1:0] bits.

The timer frequency can be fCPU/2, fCPU/4, fCPU/8

or an external frequency.

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