ST7265X datasheet(73/166 Pages) STMICROELECTRONICS

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ST7265x

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USB INTERFACE (Cont’d)

Bit 2 = PDWN

Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, soft-

ware should allow at least 3

µs for stabilisation of

the power supply before using the USB interface.

Bit 1 = FSUSP

Force suspend mode.

This bit is set by software to enter Suspend mode.

The ST7 should also be put in Halt mode to reduce

power consumption.

0: Suspend mode inactive

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Bit 0 = FRES

Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

0: Reset not forced

1: USB interface reset forced.

The USB interface is held in RESET state until

software clears this bit, at which point a “USB-RE-

SET” interrupt will be generated if enabled.

DEVICE ADDRESS REGISTER (DADDR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 Reserved, forced by hardware to 0.

Bits 6:0 = ADD[6:0]

Device address, 7 bits.

Software must write into this register the address

sent by the host during enumeration.

Note: This register is also reset when a USB reset

is received or forced through bit FRES in the CTLR

USB STATUS REGISTER (USBSR)

Read only

Reset Value: 0000 0000 (00h)

Bits 7:6 = PID[1:0]

Token PID bits 1 & 0 for End-

point 0 Control.

USB token PIDs are encoded in four bits. PID[1:0]

correspond to the most significant bits of the PID

field of the last token PID received by Endpoint 0.

Note: The least significant PID bits have a fixed

value of 01.

When a CTR interrupt occurs on Endpoint 0 (see

PID[1:0] bits to retrieve the PID name of the token

received.

The USB specification defines PID bits as:

Bit 5 = IN/OUT

Last transaction direction for End-

point 1 or 2.

This bit is set by hardware when a CTR interrupt

occurs on Endpoint 1 or Endpoint 2.

0: OUT transaction

1: IN transaction

Bits 4:3 = EP[1:0]

Endpoint number.

These bits identify the endpoint which required at-

tention.

00 = Endpoint 0

01 = Endpoint 1

10 = Endpoint 2

ADD6ADD5ADD4ADD3ADD2ADD1ADD0

PID1

PID0

IN/

OUT

EP1

EP0

ERR2

ERR1

ERR0

PID1

PID0

PID Name

OUT

SETUP

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