PCIMX258CJM4A datasheet(106/144 Pages) FREESCALE

106 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

106

Freescale Semiconductor

3.7.17.2

SSI Receiver Timing with Internal Clock

Figure 79 shows the timing for the SSI receiver with internal clock. Table 80 describes the timing

parameters (SS1–SS51) shown in the figure.

Figure 79. SSI Receiver Internal Clock Timing Diagram

Table 80. SSI Receiver Timing with Internal Clock

Parameter

Min.

Max.

Unit

Internal Clock Operation

SS1

(Tx/Rx) CK clock period

81.4

—

SS2

(Tx/Rx) CK clock high period

36.0

—

SS3

(Tx/Rx) CK clock rise time

—

6.0

SS4

(Tx/Rx) CK clock low period

36.0

—

SS5

(Tx/Rx) CK clock fall time

—

6.0

SS7

(Rx) CK high to FS (bl) high

—

15.0

SS9

(Rx) CK high to FS (bl) low

—

15.0

SS11

(Rx) CK high to FS (wl) high

—

15.0

SS13

(Rx) CK high to FS (wl) low

—

15.0

SS20

SRXD setup time before (Rx) CK low

10.0

—

SS21

SRXD hold time after (Rx) CK low

0.0

—

Oversampling Clock Operation

SS47

Oversampling clock period

15.04

—

SS50

SS48

AUDn_TXC

AUDn_TXFS (bl)

AUDn_TXFS (wl)

AUDn_RXD

AUDn_RXC

SS1

SS4

SS2

SS51

SS20

SS21

SS49

SS7

SS9

SS11

SS13

SS47

(Output)

(Input)

(Output)

SS3

SS5

PCIMX258CJM4A Datasheet(PDF) 106 Page - Freescale Semiconductor, Inc

PCIMX258CJM4A Datasheet(HTML) 106 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL