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PCIMX258CJM4A Datasheet(PDF) 109 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A Datasheet(HTML) 109 Page - Freescale Semiconductor, Inc |
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109 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 Freescale Semiconductor 109 3.7.17.4 SSI Receiver Timing with External Clock Figure 81 shows the timing for SSI receiver with external clock. Table 82 describes the timing parameters (SS22–SS41) used in the figure. Figure 81. SSI Receiver with External Clock Timing Diagram Note: • All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. • All timings are on pads when SSI is being used for data transfer. Table 82. SSI Receiver Timing with External Clock ID Parameter Min. Max. Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS28 FS (bl) low/high setup before (Tx) CK falling –10.0 15.0 ns SS30 FS (bl) low/high setup before (Tx) CK falling 10.0 — ns SS32 FS (wl) low/high setup before (Tx) CK falling –10.0 15.0 ns SS34 FS (wl) low/high setup before (Tx) CK falling 10.0 — ns SS35 (Tx/Rx) External FS rise time — 6.0 ns SS36 (Tx/Rx) External FS fall time — 6.0 ns SS40 SRXD setup time before (Rx) CK low 10.0 — ns SS41 SRXD hold time after (Rx) CK low 2.0 — ns SS24 SS35 SS30 SS26 SS25 SS23 AUDn_TXC AUDn_TXFS (bl) AUDn_TXFS (wl) AUDn_RXD SS40 SS22 SS32 SS36 SS41 (Input) (Input) (Input) (Input) SS28 SS34 |
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