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PCIMX258CJM4A Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc

Part # PCIMX258CJM4A
Description  i.MX25 Applications Processor for Consumer and Industrial Products
PDF  144 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PCIMX258CJM4A Datasheet(HTML) 107 Page - Freescale Semiconductor, Inc

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3
Freescale Semiconductor
107
Note:
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on pads when SSI is being used for a data transfer.
• ”Tx” and “Rx” refer to the transmit and receive sections of the SSI.
• For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97
mode of operation).
3.7.17.3
SSI Transmitter Timing with External Clock
Figure 80 shows the timing for the SSI transmitter with external clock. Table 81 describes the timing
parameters (SS22-SS46) shown in the figure.
Figure 80. SSI Transmitter with External Clock Timing Diagram
SS48
Oversampling clock high period
6.0
—
ns
SS49
Oversampling clock rise time
—
3.0
ns
SS50
Oversampling clock low period
6.0
—
ns
SS51
Oversampling clock fall time
—
3.0
ns
Table 80. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min.
Max.
Unit
SS45
SS24
SS26
SS25
SS23
AUDn_TXC
AUDn_TXFS (bl)
AUDn_TXFS (wl)
AUDn_TXD
AUDn_RXD
Note: SRXD Input in Synchronous mode only
SS22
SS44
SS39
SS38
SS37
SS46
(Input)
(Input)
(Input)
(Output)
(Input)
SS29
SS27
SS31
SS33



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