MC9S08DN60F1CLF datasheet(205/356 Pages) FREESCALE

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Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

205

11.4.1.3

Data Transfer

Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction

speciﬁed by the R/W bit sent by the calling master.

All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address

information for the slave device

Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while

SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the msb being

transferred ﬁrst. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the

receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one

complete data transfer needs nine clock pulses.

If the slave receiver does not acknowledge the master in the ninth bit time, the SDA line must be left high

by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.

If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave

interprets this as an end of data transfer and releases the SDA line.

In either case, the data transfer is aborted and the master does one of two things:

•

Relinquishes the bus by generating a stop signal.

•

Commences a new calling by generating a repeated start signal.

11.4.1.4

Stop Signal

The master can terminate the communication by generating a stop signal to free the bus. However, the

master may generate a start signal followed by a calling command without generating a stop signal ﬁrst.

This is called repeated start. A stop signal is deﬁned as a low-to-high transition of SDA while SCL at

logical 1 (see Figure 11-9).

The master can generate a stop even if the slave has generated an acknowledge at which point the slave

must release the bus.

11.4.1.5

Repeated Start Signal

As shown in Figure 11-9, a repeated start signal is a start signal generated without ﬁrst generating a stop

signal to terminate the communication. This is used by the master to communicate with another slave or

with the same slave in different mode (transmit/receive mode) without releasing the bus.

11.4.1.6

Arbitration Procedure

The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or

more masters try to control the bus at the same time, a clock synchronization procedure determines the bus

clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest

one among the masters. The relative priority of the contending masters is determined by a data arbitration

procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The

losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,

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