MC9S08DN60F1CLF datasheet(202/356 Pages) FREESCALE

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Chapter 11 Inter-Integrated Circuit (S08IICV2)

MC9S08DN60 Series Data Sheet, Rev 3

202

Freescale Semiconductor

11.3.5

IIC Data I/O Register (IICD)

NOTE

When transitioning out of master receive mode, the IIC mode should be

switched before reading the IICD register to prevent an inadvertent

initiation of a master receive data transfer.

In slave mode, the same functions are available after an address match has occurred.

The TX bit in IICC must correctly reﬂect the desired direction of transfer in master and slave modes for

the transmission to begin. For instance, if the IIC is conﬁgured for master transmit but a master receive is

desired, reading the IICD does not initiate the receive.

Reading the IICD returns the last byte received while the IIC is conﬁgured in master receive or slave

receive modes. The IICD does not reﬂect every byte transmitted on the IIC bus, nor can software verify

that a byte has been written to the IICD correctly by reading it back.

In master transmit mode, the ﬁrst byte of data written to IICD following assertion of MST is used for the

address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required

R/W bit (in position bit 0).

11.3.6

IIC Control Register 2 (IICC2)

76543210

DATA

Reset

00000000

Figure 11-7. IIC Data I/O Register (IICD)

Table 11-7. IICD Field Descriptions

Field

Description

7–0

DATA

Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most signiﬁcant

bit is sent ﬁrst. In master receive mode, reading this register initiates receiving of the next byte of data.

76543210

GCAEN

ADEXT

000

AD10

AD9

AD8

Reset

00000000

= Unimplemented or Reserved

Figure 11-8. IIC Control Register (IICC2)

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