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Chapter 13 Serial Communications Interface (S08SCIV4)

MC9S08DN60 Series Data Sheet, Rev 3

234

Freescale Semiconductor

13.2

The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for

transmit/receive data.

Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address

assignments for all SCI registers. This section refers to registers and control bits only by their names. A

Freescale-provided equate or header ﬁle is used to translate these names into the appropriate absolute

addresses.

13.2.1

SCI Baud Rate Registers (SCI1BDH, SCI1BDL)

This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud

rate setting [SBR12:SBR0], ﬁrst write to SCI1BDH to buffer the high half of the new value and then write

to SCI1BDL. The working value in SCI1BDH does not change until SCI1BDL is written.

SCI1BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the ﬁrst

time the receiver or transmitter is enabled (RE or TE bits in SCI1C2 are written to 1).

76543210

LBKDIE

RXEDGIE

SBR12

SBR11

SBR10

SBR9

SBR8

Reset

00000000

= Unimplemented or Reserved

Figure 13-4. SCI Baud Rate Register (SCI1BDH)

Table 13-1. SCI1BDH Field Descriptions

Field

Description

LBKDIE

LIN Break Detect Interrupt Enable (for LBKDIF)

0 Hardware interrupts from LBKDIF disabled (use polling).

1 Hardware interrupt requested when LBKDIF ﬂag is 1.

RXEDGIE

RxD Input Active Edge Interrupt Enable (for RXEDGIF)

0 Hardware interrupts from RXEDGIF disabled (use polling).

1 Hardware interrupt requested when RXEDGIF ﬂag is 1.

4:0

SBR[12:8]

Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the

modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to

reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16

×BR). See also BR bits in

Table 13-2.

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