MC9S08DN60F1CLF datasheet(237/356 Pages) FREESCALE

237 / 356 page

Chapter 13 Serial Communications Interface (S08SCIV4)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

237

13.2.4

SCI Status Register 1 (SCI1S1)

This register has eight read-only status ﬂags. Writes have no effect. Special software sequences (which do

not involve writing to this register) are used to clear these status ﬂags.

Transmitter Enable

0 Transmitter off.

1 Transmitter on.

TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output

for the SCI system.

When the SCI is conﬁgured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of

trafﬁc on the single SCI communication line (TxD pin).

TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.

Refer to Section 13.3.2.1, “Send Break and Queued Idle” for more details.

When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued

break character ﬁnishes transmitting before allowing the pin to revert to a general-purpose I/O pin.

Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin.

If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.

0 Receiver off.

1 Receiver on.

RWU

Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it

waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle

line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most signiﬁcant data bit in a character

(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware

condition automatically clears RWU. Refer to Section 13.3.3.2, “Receiver Wakeup Operation” for more details.

0 Normal SCI receiver operation.

1 SCI receiver in standby waiting for wakeup condition.

SBK

Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional

break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.

Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a

second break character may be queued before software clears SBK. Refer to Section 13.3.2.1, “Send Break and

Queued Idle” for more details.

0 Normal transmitter operation.

1 Queue break character(s) to be sent.

76543210

TDRE

RDRF

IDLE

Reset

11000000

= Unimplemented or Reserved

Figure 13-8. SCI Status Register 1 (SCI1S1)

Table 13-4. SCI1C2 Field Descriptions (continued)

Field

Description

MC9S08DN60F1CLF Datasheet(PDF) 237 Page - Freescale Semiconductor, Inc

MC9S08DN60F1CLF Datasheet(HTML) 237 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL