MC9S08DN60F1CLF datasheet(240/356 Pages) FREESCALE

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Chapter 13 Serial Communications Interface (S08SCIV4)

MC9S08DN60 Series Data Sheet, Rev 3

240

Freescale Semiconductor

When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by

one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data

character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This

would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When

the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits

to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.

13.2.6

SCI Control Register 3 (SCI1C3)

LBKDE

LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While

LBKDE is set, framing error (FE) and receive data register full (RDRF) ﬂags are prevented from setting.

0 Break character is detected at length of 10 bit times (11 if M = 1).

1 Break character is detected at length of 11 bit times (12 if M = 1).

RAF

Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is

cleared automatically when the receiver detects an idle line. This status ﬂag can be used to check whether an

SCI character is being received before instructing the MCU to go to stop mode.

0 SCI receiver idle waiting for a start bit.

1 SCI receiver active (RxD input not idle).

1 Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

76543210

RR8

TXDIR

TXINV

ORIE

NEIE

FEIE

PEIE

Reset

00000000

= Unimplemented or Reserved

Figure 13-10. SCI Control Register 3 (SCI1C3)

Table 13-7. SCI1C3 Field Descriptions

Field

Description

Ninth Data Bit for Receiver — When the SCI is conﬁgured for 9-bit data (M = 1), R8 can be thought of as a

ninth receive data bit to the left of the MSB of the buffered data in the SCI1D register. When reading 9-bit data,

read R8 before reading SCI1D because reading SCI1D completes automatic ﬂag clearing sequences which

could allow R8 and SCI1D to be overwritten with new data.

Ninth Data Bit for Transmitter — When the SCI is conﬁgured for 9-bit data (M = 1), T8 may be thought of as a

ninth transmit data bit to the left of the MSB of the data in the SCI1D register. When writing 9-bit data, the entire

9-bit value is transferred to the SCI shift register after SCI1D is written so T8 should be written (if it needs to

change from its previous value) before SCI1D is written. If T8 does not need to change in the new value (such

as when it is used to generate mark or space parity), it need not be written each time SCI1D is written.

TXDIR

TxD Pin Direction in Single-Wire Mode — When the SCI is conﬁgured for single-wire half-duplex operation

(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.

0 TxD pin is an input in single-wire mode.

1 TxD pin is an output in single-wire mode.

Table 13-6. SCI1S2 Field Descriptions (continued)

Field

Description

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