MC9S08DN60F1CLF datasheet(159/356 Pages) FREESCALE

159 / 356 page

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

159

Figure 8-13. Trim Procedure

In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing ﬁnal

test with automated test equipment. A separate signal or message is provided to the MCU operating under

user provided software control. The MCU initiates a trim procedure as outlined in Figure 8-13 while the

tester supplies a precision reference signal.

If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using

a reference divider value (RDIV setting) of twice the ﬁnal value. After the trim procedure is complete, the

reference divider can be restored. This will prevent accidental overshoot of the maximum clock frequency.

Initial conditions:

1) Clock supplied from ATE has 500

μs duty period

2) MCG configured for internal reference with 8MHz bus

START TRIM PROCEDURE

CONTINUE

CASE STATEMENT

COUNT > EXPECTED = 500

MEASURE

INCOMING CLOCK WIDTH

TRMVAL = $100

COUNT < EXPECTED = 500

COUNT = EXPECTED = 500

TRMVAL =

TRMVAL - 256/ (2**n)

TRMVAL + 256/ (2**n)

n = n + 1

(COUNT = # OF BUS CLOCKS / 8)

(DECREASING TRMVAL

INCREASES THE FREQUENCY)

(INCREASING TRMVAL

DECREASES THE FREQUENCY)

YES

IS n > 9?

(RUNNING TOO SLOW)

(RUNNING TOO FAST)

n=1

STORE MCGTRM AND

FTRIM VALUES IN

NON-VOLATILE MEMORY

MC9S08DN60F1CLF Datasheet(PDF) 159 Page - Freescale Semiconductor, Inc

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