68HC05CL48 datasheet(4/145 Pages) MOTOROLA

4 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

MC68HC05CL48

REV 2.0

TABLE OF CONTENTS

Section

Page

SECTION 3

CPU

3.1

REGISTERS .................................................................................................... 3-1

3.1.1

Accumulator (A) ........................................................................................... 3-1

3.1.2

Index Register (X)........................................................................................ 3-2

3.1.3

Stack Pointer (SP) ....................................................................................... 3-2

3.1.4

Program Counter (PC)................................................................................. 3-2

3.1.5

Condition Code Register (CCR) .................................................................. 3-3

SECTION 4

INTERRUPTS

4.1

RESET INTERRUPT SEQUENCE .................................................................. 4-3

4.2

SOFTWARE INTERRUPT (SWI) ..................................................................... 4-3

4.3

HARDWARE INTERRUPTS ............................................................................ 4-3

4.3.1

External Interrupt (IRQ) ............................................................................... 4-3

4.3.2

External Interrupts (IRQ0, IRQ1, IRQ2, KBI[3:7]) ........................................ 4-6

4.3.3

Caller ID Interrupt (RDI/CDI,CDRI).............................................................. 4-8

4.3.4

TIMER Interrupt ........................................................................................... 4-8

4.3.5

SPI Interrupt................................................................................................. 4-9

4.3.6

CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer).......................... 4-9

SECTION 5

RESETS

5.1

EXTERNAL RESET (RESET).......................................................................... 5-1

5.2

POWER-ON RESET (POR)............................................................................. 5-1

5.3

COMPUTER OPERATING PROPERLY RESET (COPR) ............................... 5-2

SECTION 6

LOW POWER MODES

6.1

LOW-POWER MODES .................................................................................... 6-1

6.1.1

STOP Instruction ......................................................................................... 6-1

6.1.2

WAIT Instruction .......................................................................................... 6-1

6.2

DATA-RETENTION MODE.............................................................................. 6-2

6.3

COP WATCHDOG TIMER CONSIDERATIONS ............................................. 6-2

SECTION 7

INPUT/OUTPUT PORTS

7.1

PARALLEL PORTS.......................................................................................... 7-1

7.2

PORT A............................................................................................................ 7-2

7.3

PORT B............................................................................................................ 7-2

7.4

PORT C............................................................................................................ 7-2

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