68HC05CL48 datasheet(68/145 Pages) MOTOROLA

68 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

TIMER

MC68HC05CL48

8-16

REV 2.0

8.2.1 Computer Operating Properly (COP) Watchdog reset

The COP watchdog timer function is implemented on this device by using the

output of the RTI circuit and further dividing it by eight. The minimum COP reset

rates are listed in Table 8-1. If the COP circuit times out, an internal reset is

generated and the normal reset vector is fetched.

Preventing a COP time-out is done by writing a “0” to bit 0 of address $FFF0. This

location is shared with User ROM byte. And reading this location will return the

User ROM data. When the COP is cleared, only the ﬁnal divide by eight stage

(output of the RTI) is cleared. If the COP (Computer Operating Properly)

Watchdog Timer circuit times out, an internal reset is generated and the reset

vector is fetched.

This function is software selectable by setting the COP bit in the Option Register.

The COP bit is set after reset, i.e. the COP function is defaulted. The COP

function can be disable by writing a ‘0’ to this bit.

NOTE

COP is located at bit 6 of the Option Register at $001F, which can

only be written once after reset.

8.2.2 Ctimer Control and Status Register (CTCSR)

The CTCSR contains the timer interrupt ﬂag, the timer interrupt enable bits, and

the real time interrupt rate select bits.

CTOF - Core Timer Over Flow

This is a clearable, read-only status bit and is set when the 8-bit ripple counter

rolls over from $FF to $00.

1 =

No effect

0 =

Clearing the TOF

RTIF - Real Time Interrupt Flag

The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4

selector. The clock frequency that drives the RTI circuit is E/213 with three

additional divider stages. This ﬂag is a clearable, read-only status bit and is set

76543210

CTCSR

$0008

READ

CTOF

RTIF

CTOFE

RTIE

RT1

RT0

WRITE

RESET

00000011

68HC05CL48 Datasheet(PDF) 68 Page - Motorola, Inc

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