68HC05CL48 datasheet(78/145 Pages) MOTOROLA

78 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

SERIAL PERIPHERAL INTERFACE

MC68HC05CL48

9-6

REV 2.0

9.2.2 SPSR SPI Status Register

SPIF SPI Interrupt Request

SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by

reading the SPSR register (with SPIF set) followed by an access (read or write)

to the SPI Data Register.

WCOL Write Collision Status Flag

This error status ﬂag is used to indicate that a serial transfer was in progress

when the MCU tried to write new data into the SPDR data register. The MCU

write is disabled to avoid writing over the data being transmitted. No interrupt is

generated because the error status ﬂag can be read upon completion of the

transfer that was in progress at the time of the error. This ﬂag is automatically

cleared by a read of the SPSR (with WCOL set) followed by an access (read or

write) to the SPDR register.

MODFSPI Mode Error Interrupt Status Flag

This bit is set automatically by SPI hardware if the MSTR control bit is set to

one and the Slave Select input pin becomes zero. This condition is not

permitted in normal operation. This ﬂag is automatically cleared by a read of

the SPSR (with MODF set) followed by a write to the SPCR register.

9.2.3 SPDR SPI Data Register

This 8-bit register is both the input and output register for SPI data. In the SPI

system the 8-bit data register in the master and the 8-bit data register in the slave

are linked by the MOSI and MISO wires to form a distributed 16-bit register. When

a data transfer operation is performed, this 16-bit register is serially shifted eight

bit positions by the SCK clock from the master so the data is effectively

76543210

SPSR

$0021

READ

SPIF

WCOL

MODF

0000

WRITE

RESET

00000000

76543210

SPDR

$0022

READ

SPD7

SPD6

SPD5

SPD4

SPD3

SPD2

SPD1

SPD0

WRITE

RESET

UUUUUUUU

68HC05CL48 Datasheet(PDF) 78 Page - Motorola, Inc

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