68HC05CL48 datasheet(64/145 Pages) MOTOROLA

64 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

TIMER

MC68HC05CL48

8-12

REV 2.0

IC1IE - Input Capture 1 Interrupt Enable

1 =

Interrupt enabled

0 =

Interrupt disabled

IC2IE - Input Capture 2 Interrupt Enable

1 =

Interrupt enabled

0 =

Interrupt disabled

OC1IE - Output Compare 1 Interrupt Enable

1 =

Interrupt enabled

0 =

Interrupt disabled

OC2IE - Output Compare 2 Interrupt Enable

1 =

Interrupt enabled

0 =

Interrupt disabled

TOIE - Timer Overﬂow Interrupt Enable

1 =

Interrupt enabled

0 =

Interrupt disabled

IEDG2 - Input Edge 2

Value of the input edge determines which level transition on TCAP2 pin will

trigger a free running counter transfer to the input capture register. Reset does

not affect the IEDG2 bit.

1 =

positive edge

0 =

negative edge

IEDG1 - Input Edge

Value of the input edge determines which level transition on TCAP1 pin will

trigger a free running counter transfer to the input capture register. Reset does

not affect the IEDG1 bit.

1 =

positive edge

0 =

negative edge

8.1.5 Timer Status Register (TSR)

The timer status register is a read-only register and is illustrated below followed by

a deﬁnition of each bit. Refer to timing diagrams shown in Figure 8-3, Figure 8-2

and Figure 8-4 for timing relationship to the timer status register bits.

76543210

TSR

$0012

READ

IC1F

IC2F

OC1F

OC2F

TOF

WRITE

RESET

UUUUUUU

U = UNAFFECTED

68HC05CL48 Datasheet(PDF) 64 Page - Motorola, Inc

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