68HC05CL48 datasheet(60/145 Pages) MOTOROLA

Part #	68HC05CL48

Description	SPECIFICATION (General Release)

PDF	145 Pages

Scroll/Zoom	100%

Manufacturer	MOTOROLA [Motorola, Inc]

Direct Link	http://www.freescale.com

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GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

TIMER

MC68HC05CL48

8-8

REV 2.0

Figure 8-4. Timer State Timing Diagram For Output Compare

8.1.3 Input Capture Registers

8.1.3.1

Input Capture Register 1

76543210

IC1H

$0013

READ

IC1:15

IC1:14

IC1:13

IC1:12

IC1:11

IC1:10

IC1:9

IC1:8

WRITE

RESET

UUUUUUUU

Internal Processor Clock

Internal

Timer

Clocks

T00

T01

T10

T11

Counter (16 bit)

Compare Register Latch

$FFEB

$FFEC

$FFED

$FFEE

1. The CPU writes to the Compare Register may take place at any time, but a compare

$FFEF

Compare Register

CPU writes $FFED

$FFED

Output Compare Flag (OCF)

2. Internal compare takes place during timer state T01.

3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this

only occurs at timer state T01. Thus, a 4-cycle different may exist between the write

to the Compare Register and the actual compare.

example).

68HC05CL48 Datasheet(PDF) 60 Page - Motorola, Inc

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