68HC705SB7 datasheet(36/170 Pages) FREESCALE

36 / 170 page

GENERAL RELEASE SPECIFICATION

August 27, 1998

MOTOROLA

INTERRUPTS

MC68HC05SB7

4-6

REV 2.1

IRQE — External Interrupt Request Enable

This read/write bit enables external interrupts. Reset sets the IRQE bit.

1 =

External interrupt processing enabled.

0 =

External interrupt processing disabled.

VCOEN — VCO Enable

Please refer to section on System Clock.

LEVEL — External Interrupt Sensitivity

This bit makes the external interrupt inputs level-triggered as well as edge-trig-

gered.

1 =

IRQ/VPP pin negative edge-triggered and low level-triggered.

0 =

IRQ/VPP pin negative edge-triggered only.

IRQF — External Interrupt Request Flag

The IRQ ﬂag is a clearable, read-only bit that is set when an external interrupt

request is pending. Reset clears the IRQF bit.

1 =

Interrupt request pending.

0 =

No interrupt request pending.

The following condition set the IRQ ﬂag:

•

An external interrupt signal on the IRQ/VPP pin.

The following conditions clear the IRQ ﬂag:

•

When the CPU fetches the interrupt vector.

•

When a logic “1” is written to the IRQR bit.

IRQR — Interrupt Request Reset

This write-only bit clears the IRQF ﬂag bit and prevents redundant execution of

interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic

zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no

affect on IRQR.

1 =

Clear IRQF ﬂag bit.

0 =

No effect.

4.5

CORE TIMER INTERRUPTS

The Core Timer can generate the following interrupts:

•

Timer overﬂow interrupt.

•

Real-time interrupt.

Setting the I bit in the condition code register disables Core Timer interrupts. The

controls and ﬂags for these interrupts are in the Core Timer status and control reg-

ister (CTSCR) located at $0008.

68HC705SB7 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

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