68HC705SB7 datasheet(10/170 Pages) FREESCALE

10 / 170 page

GENERAL RELEASE SPECIFICATION

August 27, 1998

MOTOROLA

MC68HC05SB7

viii

REV 2.1

LIST OF FIGURES

Figure

Title

Page

11-1

PWM Block Diagram ...................................................................................... 11-1

11-2

D/A Data Register 0 (DAC0) (MSB) ............................................................... 11-2

11-3

D/A Data Register 0 (DAC0) (LSB) ................................................................ 11-2

11-4

D/A Data Register 1 (DAC1) (MSB) ............................................................... 11-2

11-5

D/A Data Register 1 (DAC1) (LSB) ................................................................ 11-2

11-6

D/A Data Register 2 (DAC2) (MSB) ............................................................... 11-2

11-7

D/A Data Register 2 (DAC2) (LSB) ................................................................ 11-2

11-10 PWM Output Waveform Examples ................................................................ 11-3

11-8

D/A Data Register 3 (DAC3) (MSB) ............................................................... 11-3

11-9

D/A Data Register 3 (DAC3) (LSB) ................................................................ 11-3

11-11 MUX Channel Enable Register (MCER) ........................................................ 11-4

12-1

SM-Bus Interface Block Diagram ................................................................... 12-2

12-2

SM-Bus Transmission Signal Diagram .......................................................... 12-3

12-3

Clock Synchronization.................................................................................... 12-5

12-4

Miscellaneous Control Register (MCR)........................................................ 12-10

12-5

Flow-chart of SM-Bus Interrupt Routine....................................................... 12-12

13-1

Current Sense Amplifier Block ....................................................................... 13-2

13-2

CSA Status and Control Register (CSSCR)................................................... 13-3

13-3

Miscellaneous Control Register (MCR).......................................................... 13-4

14-1

Miscellaneous Control Register (MCR).......................................................... 14-1

14-2

External Temperature Sensor Connection..................................................... 14-2

15-1

Analog Subsystem Block Diagram................................................................. 15-2

15-2

Analog Multiplex Register 1 (AMUX1)............................................................ 15-3

15-3

Analog Multiplex Register 2 (AMUX2)............................................................ 15-3

15-4

INV Bit Action ................................................................................................. 15-4

15-5

Analog Control Register (ACR) .................................................................... 15-14

15-6

Analog Status Register ................................................................................ 15-17

15-7

Single-Slope A/D Conversion Method.......................................................... 15-19

15-8

A/D Conversion - Full Manual Control (Mode 0) .......................................... 15-23

15-9

A/D Conversion - Manual/Auto Discharge Control (Mode 1) ....................... 15-24

15-10 A/D Conversion - TOF/ICF Control (Mode 2)............................................... 15-25

15-11 A/D Conversion - OCF/ICF Control (Mode 3) .............................................. 15-26

16-1

Personality EPROM ....................................................................................... 16-1

16-2

PEPROM Bit Select Register (PEBSR) ......................................................... 16-2

16-3

PEPROM Status and Control Register (PESCR)........................................... 16-2

18-1

Stop Recovery Timing Diagram ..................................................................... 18-6

18-2

Internal Reset Timing Diagram ...................................................................... 18-7

18-3

Low Voltage Reset Timing Diagram............................................................... 18-7

18-4

SM-Bus Timing Diagram ................................................................................ 18-9

A-1

MC68HC705SB7 Memory Map........................................................................A-1

A-2

MC68HC705SB7 Mask Option Register (MOR ...............................................A-2

A-3

EPROM Programming Register (EPROG).......................................................A-3

A-4

EPROM Programming Sequence ....................................................................A-5

68HC705SB7 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

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