68HC705SB7 datasheet(69/170 Pages) FREESCALE

69 / 170 page

August 27, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05SB7

16-BIT TIMER

MOTOROLA

REV 2.1

10-7

Reading the ICRH inhibits further captures until the ICRL is also read. Reading

the ICRL after reading the timer status register (TSR) clears the ICF ﬂag bit. does

not inhibit transfer of the free-running counter. There is no conﬂict between read-

ing the ICRL and transfers from the free-running timer counters. The input capture

registers always contain the free-running timer counter value which corresponds

to the most recent input capture.

NOTE

To prevent interrupts from occurring between readings of the ICRH and ICRL, set

the I bit in the condition code register (CCR) before reading ICRH and clear the I

bit after reading ICRL.

10.4

OUTPUT COMPARE REGISTERS

Figure 10-10. Timer Output Compare Block Diagram

The Output Compare function is a means of generating an output signal when the

16-bit timer counter reaches a selected value as shown in Figure 10-10. Software

writes the selected value into the output compare registers. On every fourth inter-

nal clock cycle (every eight oscillator clock cycle) the output compare circuitry

compares the value of the free-running timer counter to the value written in the

output compare registers. When a match occurs, the timer transfers the output

level (OLVL) from the timer control register (TCR) to the TCMP.

OCRH ($0016)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OUTPUT COMPARE

RESET

CLOCK

INTERRUPT

OCRL ($0017)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

R/W

OCRH

R/W

OCRL

BUS

EDGE

SELECT

DETECT

LOGIC

16-BIT COMPARATOR

(OCF)

TCMP

68HC705SB7 Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc

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