68HC705SB7 datasheet(60/170 Pages) FREESCALE

60 / 170 page

GENERAL RELEASE SPECIFICATION

August 27, 1998

MOTOROLA

CORE TIMER

MC68HC05SB7

9-4

REV 2.1

Power on clears the entire counter chain and begins clocking the counter. After

the startup delay (16 or 4064 internal clock cycles) the power on reset circuit is

released, clearing the counter again and allowing the MCU to come out of reset.

Each count of the timer counter register takes eight oscillator cycles or four cycles

of the internal clock. A timer overﬂow function at the eighth counter stage allows a

timer interrupt every 1024 internal clock cycles.

9.3

COP WATCHDOG

Four counter stages at the end of the Core Timer make up the computer operating

properly (COP) watchdog. The COP watchdog timeout period is shown in Table 9-

A timeout of the COP watchdog generates a COP reset. The COP watchdog is

part of a software error detection system and must be cleared periodically to start

a new timeout period. To clear the COP watchdog and prevent a COP reset, write

a logic “0” to the COPC bit of the COP register at location $1FF0.

COPC — COP Clear

COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the

COP watchdog from resetting the MCU. Reset clears the COPC bit.

1 =

No effect on system.

0 =

Reset COP watchdog timer.

The COP Watchdog reset will assert the pulldown device to pull the RESET pin

low for three to four clock cycles of the internal bus clock.

After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic

“1” to the COPON bit in the Miscellaneous Control Register (see Figure 9-5).

Once enabled, the COP watchdog can only be disabled by a POR or reset.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

COPR

00000000

$1FF0

COPC

reset:

UUUUUUU

U = UNAFFECTED BY RESET

Figure 9-4. COP Watchdog Register (COPR)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MCR

TSEN

LVRON

SCLK

CSSEL

TCSEL

ESVEN

SMINLEV

$000B

COPON

reset:

01000000

U = UNAFFECTED BY RESET

Figure 9-5. Miscellaneous Control Register (MCR)

68HC705SB7 Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc

68HC705SB7 Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL