68HC705SB7 datasheet(80/170 Pages) FREESCALE

80 / 170 page

GENERAL RELEASE SPECIFICATION

August 27, 1998

MOTOROLA

SM-BUS

MC68HC05SB7

12-2

REV 2.1

Figure 12-1. SM-Bus Interface Block Diagram

12.3

SM-BUS SYSTEM CONFIGURATION

The SM-Bus system uses a serial data line (SDA) and a serial clock line (SCL) for

data transfer. All devices connected to it must have open drain or open collector

outputs and the logical “AND” function is performed on both lines by two pull up

resistors.

12.4

SM-BUS PROTOCOL

Normally a standard communication is composed of four parts, START signal,

Slave Address transmission, Data transfer, and STOP signal. These are described

brieﬂy in the following sections and illustrated in Figure 12-2.

Internal bus

Frequency

divider

Address

comparator

Address

SMEN SMIEN SMSTA SMTX TXAK

SMCF SMAAS SMBB SMAL

SRW

SMIF SRXAK

TX shift

RX shift

control

M-Bus

interrupt

SCL

control

SDA

control

M-Bus clock

generator

sync logic

START, STOP

detector and

arbitration

START, STOP

generator and

timing sync

SCL

SDA

Control register

Status register

Interrupt

68HC705SB7 Datasheet(PDF) 80 Page - Freescale Semiconductor, Inc

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