ADSP-21469KBZ-ENG2 datasheet(5/56 Pages) AD

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ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 5 of 56

November 2008

FAMILY CORE ARCHITECTURE

The ADSP-21469 is code compatible at the assembly level with

the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and

ADSP-21161, and with the first generation ADSP-2106x

SHARC processors. The ADSP-21469 shares architectural fea-

tures with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and

ADSP-2116x SIMD SHARC processors, as detailed in the fol-

lowing sections.

SIMD Computational Engine

The ADSP-21469 contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21469 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on page 1). With the ADSP-21469’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a sin-

gle cycle.

Instruction Cache

The ADSP-21469 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21469’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21469 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21469 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

Variable Instruction Set Architecture

In addition to supporting the standard 48-bit instructions from

previously existing SHARC family of processors, the ADSP-

21469 will support new instructions of 16 and 32 bits in addition

to the existing 48 bit instructions. This feature, called Variable

Instruction Set Architecture (VISA), is based on dropping

redundant/unused bits within the 48-bit instruction to create

more efficient and compact code. The program sequencer will

now support fetching these 16-bit and 32-bit instructions as well

in addition to the standard 48-bit instructions, both from inter-

nal as well as external memory. Source modules will need to be

built using the VISA option, in order to allow code generation

tools to create these more efficient opcodes.

FFT Accelerator

FFT accelerator implements radix-2 complex/real input, com-

plex output FFT with no core intervention.

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