ADSP-21469KBZ-ENG2 datasheet(16/56 Pages) AD

16 / 56 page

Rev. PrB

Page 16 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

SPECIFICATIONS

OPERATING CONDITIONS

Parameter1

1 Specifications subject to change without notice.

Description

Min

Max

Unit

VDD_INT

Internal (Core) Supply Voltage

TBD2

2 The expected value is 1.1V and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.15V +/-50mV

TBD2

VDD_EXT

External (I/O) Supply Voltage

3.14

3.46

VDD_DDR2

3 Applies to DDR2 signals.

DDR2 Controller Supply Voltage

1.71

1.89

VREF

DDR2 Reference Voltage

0.84

0.96

VIH

4 Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, CLKOUT (RUNRSTIN), RESET,

TCK, TMS, TDI, TRST.

High Level Input Voltage @ VDD_EXT = max

2.0

3.6

VIL

Low Level Input Voltage @ VDD_EXT = min

-0.3

0.8

VIH_CLKIN

5 Applies to input pin CLKIN.

High Level Input Voltage @ VDD_EXT = max

TBD

VIL_CLKIN

Low Level Input Voltage @ VDD_EXT = min

TBD

VIL_DDR2

Low Level Input Voltage

-0.3

VREF - 0.12

VIH_DDR2

High Level Input Voltage

VREF + 0.13

VDD_DDR2 + 0.3

TJUNCTION

Junction Temperature 208-Lead PBGA @ TAMBIENT 08C to +708C

125

ADSP-21469KBZ-ENG2 Datasheet(PDF) 16 Page - Analog Devices

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