ADSP-21469KBZ-ENG2 datasheet(13/56 Pages) AD

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ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 13 of 56

November 2008

DDR2_CKE

O/T

High-Z/

Driven low

DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2

CKE signal.

DDR2_CS3-0

O/T

High-Z/

Driven

high

DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven

high. DDR2_CS3-0 are decoded emory address lines. Each DDR2_CS3-0lines

select the corresponding bank.

DDR2_DATA15-0

I/O/T

High-Z

DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.

DDR2_DM1-0

O/T

High-Z/

Driven

high

DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled

on both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA

7–0 and DM1 corresponds to DDR2_DATA 15–8.

DDR2_DQS1-0

I/O/T (Differential)

High-Z

Data Strobe. Output with Write Data. Input with Read Data. DQS0 corre-

sponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8.

DDR2_RAS

O/T

High-Z/

Driven

high

DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction with

other DDR2 command pins, defines the operation for the DDR2 to perform.

DDR2_WE

O/T

High-Z/

Driven

high

DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with other

DDR2 command pins, defines the operation for the DDR2 to perform

DDR2_CLK0,

DDR2_CLK1,

DDR2_CLK1

O/T (Differential)

High-Z/

driven low

DDR2 Clock. Free running, minimum frequency not guaranteed during reset.

DDR2_ODT

O/T

High-Z/

Driven low

DDR2 On Die Termination. ODT pin when driven high (along with other

requirements) enables the DDR2 termination resistances.

AMI_MS0–1

O/T

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for

the corresponding banks of external memory on the AMI interface. The MS1-

0 lines are decoded memory address lines that change at the same time as the

other address lines. When no external memory access is occurring the MS1-0

lines are inactive; they are active however when a conditional memory access

instruction is executed, whether or not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information,

see the ADSP-2146x SHARC Processor Hardware Reference.

FLAG[0]/IRQ0

I/O

High-Z

FLAG0/Interrupt Request0.

FLAG[1]/IRQ1

I/O

High-Z

FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

AMI_MS2

I/O

High-Z

FLAG2/Interrupt Request2/Async Memory Select2.

FLAG[3]/TIMEX P/

AMI_MS3

I/O

High-Z

FLAG3/Timer Expired/Async Memory Select3.

LDAT07–0

LDAT17-0

I/0

High-Z

Link Port Data (Link Ports 0-1).

LCLK0

LCLK1

I/O

High-Z

Link Port Clock (Link Ports 0–1).

LACK0

LACK1

I/O

High-Z

Link Port Acknowledge (Link Port 0-1).

THD_P

Thermal Diode Anode

THD_M

Thermal Diode Cathode

TDI

I (pu)

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI

has a fixed internal pull-up resistor1, 2.

TDO

O /T

High-Z

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS

I (pu)

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

fixed internal pull-up resistor1, 2.

Table 6. Pin List (Continued)

Name

Type

LVTTL SSTL18

State

During

and After

Reset

Description

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