ADSP-21469KBZ-ENG2 datasheet(22/56 Pages) AD

22 / 56 page

Rev. PrB

Page 22 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Clock Input

Clock Signals

The ADSP-21469 can use an external clock or a crystal. See the

CLKIN pin description in Table 6. The programmer can config-

ure the ADSP-21469 to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 6 shows the component connections used for a crystal

operating in fundamental mode. Note that the clock rate is

achieved using a 28.125 MHz crystal and a PLL multiplier ratio

16:1 (CCLK:CLKIN achieves a clock speed of 450 MHz). To

achieve the full core clock rate, programs need to configure the

multiplier bits in the PMCTL register.

Table 14. Clock Input

Parameter

450 MHz

Unit

Min

Max

Timing Requirements

tCK

CLKIN Period

TBD1

1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

TBD2

2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

tCKL

CLKIN Width Low

TBD1

TBD2

tCKH

CLKIN Width High

TBD1

TBD2

tCKRF

CLKIN Rise/Fall (0.4 V to 2.0 V)

TBD

tCCLK

3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

CCLK Period

2.221

TBD

Figure 5. Clock Input

CLKIN

CKH

CKL

Figure 6. 450 MHz Operation (Fundamental Mode Crystal)

22pF

1M *

XTAL

CLKIN

22pF

28.125 MHz

47 *

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’SSPECIFICATIONS

*TYPICAL VALUES

ADSP-21469

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