ADSP-21469KBZ-ENG2 datasheet(6/56 Pages) AD

6 / 56 page

Rev. PrB

Page 6 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

FIR Accelerators

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerators

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

MEMORY

The ADSP-21469 adds the following architectural features to

the SIMD SHARC family core.

On-Chip Memory

The ADSP-21469 contains 5 Mbits of internal RAM. Each block

can be configured for different combinations of code and data

storage (see Table 3). Each memory block supports single-cycle,

independent accesses by the core processor and I/O processor.

The ADSP-21469 memory architecture, in combination with its

separate on-chip buses, allow two data transfers from the core

and one from the I/O processor, in a single cycle.

The ADSP-21469’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabit. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory map in Table 3 displays the internal memory

address space of the ADSP-21469.

The 48-bit space section describes what this address range looks

like to an instruction that retrieves 48-bit memory.

The 32-bit section describes what this address range looks like

to an instruction that retrieves 32-bit memory.

EXTERNAL MEMORY

The external port on the ADSP-21469 SHARC provides a high

performance, glueless interface to a wide variety of industry-

standard memory devices. The external port may be used to

interface to synchronous and/or asynchronous memory devices

through the use of its separate internal memory controllers: the

16-bit DDR2 DRAM controller for connection of industry-stan-

dard synchronous DRAM devices, while the second is an 8-bit

asynchronous memory controller intended to interface to a

variety of memory devices. Four memory select pins enable up

Table 3. ADSP-21469 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 bits)

Extended Precision Normal or

Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 RAM

0x0004 9000–0x0004 EFFF

BLOCK 0 RAM

0x0008 C000-0x0009 3FFF

BLOCK 0 RAM

0x0009 2000-0x0009 DFFF

BLOCK 0 RAM

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0005 8FFF

Reserved

0x0009 E000–0x000B 1FFF

Reserved

0x0009 E000–0x000B 1FFF

Reserved

0x0013 C000–0x0016 3FFF

BLOCK 1 RAM

0x0005 9000–0x0005 EFFF

BLOCK 1 RAM

0x000A C000-0x000B 3FFF

BLOCK 1 RAM

0x000B 2000-0x000B DFFF

BLOCK 1 RAM

0x0016 4000-0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x0017 C000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 3FFF

BLOCK 2 RAM

0x000C 0000–0x000C 5554

BLOCK 2 RAM

0x000C 0000-0x000C 7FFF

BLOCK 2 RAM

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000–0x0006 FFFF

Reserved

0x000C 8000–0x000D FFFF

Reserved

0x000C 8000–0x000D FFFF

Reserved

0x0019 0000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 3FFF

BLOCK 3 RAM

0x000E 0000–0x000E 5554

BLOCK 3 RAM

0x000E 0000–0x000E 7FFF

BLOCK 3 RAM

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

Reserved

0x000E 8000–0x000F FFFF

Reserved

0x000E 8000–0x000F FFFF

Reserved

0x001D 0000–0x001F FFFF

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