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ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 19 of 56

November 2008

TIMING SPECIFICATIONS

The ADSP-21469’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, and serial ports. During reset, program the ratio between

the processor’s internal clock frequency and external (CLKIN)

clock frequency with the CLKCFG1–0 pins (see Table 9 on

Page 15). To determine switching frequencies for the serial

ports, divide down the internal clock, using the programmable

divider control of each port (DIVx for the serial ports).

Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference.

The ADSP-21469’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Core clock frequency can be calculated as:

fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN)

Note that in the user application, the PLL multiplier value

should be selected in such a way that the VCO frequency falls in

between 160 MHz and 800 MHz. The VCO frequency is calcu-

lated as follows:

fVCO = 2 × PLLM × fINPUT

where:

fVCO is the VCO frequency

PLLM is the multiplier value programmed

fINPUT is the input frequency to the PLL in MHz.

fINPUT = CLKIN when the input divider is disabled

fINPUT = CLKIN ÷ 2 when the input divider is enabled

Note the definitions of various clock periods shown in Table 12

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

Figure 3. Core Clock and System Clock Relationship to CLKIN

LOOP

FILTER

CLKIN

PCLK

DDR2_CLK

DDR2

DIVIDER

CLK_CFGx/

PMCTL

DIVIDE

BY 2

PMCTL

CCLK

PLL

XTAL

CLKIN

DIVIDER

RESETOUT/

CLKOUT

RESET

PLL

MULTIPLIER

BUF

VCO

BUF

PLLI

CLK

PMCTL

PLL

DIVIDER

CLK_CFGx/PMCTL

RESETOUT

CLKOUT

DELAY OF

4096 CLKIN

CYCLES

CORERST

PMCTL

CCLK

PCLK

CLK_CFGx/

PMCTL

LINKPORT

CLOCK

DIVIDER

PMCTL

LCLK

CLK_CFGx/

PMCTL

Table 11. CLKOUT and CCLK Clock Generation Operation

Timing

Requirements

Description

Calculation

CLKIN

Input Clock

1/tCK

CCLK

Core Clock

1/tCCLK

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