PIC16F1526 datasheet(167/354 Pages) MICROCHIP

167 / 354 page

 2011 Microchip Technology Inc.

Preliminary

DS41458A-page 167

PIC16(L)F1526/27

18.0

TIMER1/3/5 MODULE WITH

GATE CONTROL

The Timer1/3/5 module is a 16-bit timer/counter with

the following features:

• 16-bit timer/counter register pair (TMRxH:TMRxL)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Optionally synchronized comparator out

• Multiple Timer1/3/5 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle Mode

• Gate Single-pulse Mode

• Gate Value Status

• Gate Event Interrupt

Figure 18-1 is a block diagram of the Timer1/3/5 module.

FIGURE 18-1:

TIMER1/3/5 BLOCK DIAGRAM

Note:

The ‘x’ variable used in this section is

used to designate Timer1, Timer3 or

Timer5. For example, TxCON references

T1CON, T3CON or T5CON. PRx refer-

ences PR1, PR3 or PR5.

TMRxH

TMRxL

TxSYNC

TxCKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMRxIF on

Overflow

TMRx(2)

TMRxON

Note 1:

ST Buffer is high-speed type when using TxCKI.

Timer1 register increments on rising edge.

Synchronize does not operate while in Sleep.

See Table 18-4 for Timer selection.

TxG

FOSC/4

Internal

Clock

TMRxCS<1:0>

Synchronize(3)

det

Sleep input

TMRxGE

TxGPOL

TxGVAL

TxGTM

Single Pulse

Acq. Control

TxGSPM

TxGGO/DONE

TxGSS<1:0>

FOSC

Internal

Clock

LFINTOSC

T1GCON

Data Bus

det

Interrupt

TMRxGIF

Set

TxCLK

FOSC/2

Internal

Clock

TxG_IN

TMRxON

From Timer0

Timer2/4/6

Overflow

Timer10

Overflow

Overflow(4)

To Comparator Module

SOSC/TxCKI

Secondary Oscillator

(See Figure 18-2)

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