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IF_DCLK

MCLK

if_dclk_div

if_dclk_div>1

(22)

IF_DCLK

MCLK

if_dclk_div

(23)

A0[15:0]

B0[15:0]

A0[15:0]

B0[15:0]

IF_DOUT0

IF_DFSO

Mode0

IF_DCLK

IF_DFSO

Mode1

IF_DFSO

Mode2

AFE8220-Q1

www.ti.com....................................................................................................................................................... SBAS455A – JANUARY 2009 – REVISED JULY 2009

For example, bits [11:8] of dout2_config set the source assignment for time slot C2 of IF_DOUT2.

The control variable if_dclk_div sets the frequency of IF_DCLK, as shown in Equation 22 and Equation 23.

Normally the data and the frame sync change on the rising edge of IF_DCLK. If if_dclk_edge is set to 1 then

IF_DCLK is inverted so that data and frame sync change on the falling edge of IF_DCLK.

The control value if_dfso_select determines which DDC is responsible for generating IF_DFSO. If if_dfso_select

is 0, then an IF_DFSO pulse is generated each time a new output is ready from DDC0. Similarly, if if_dfso_select

is 1, then an IF_DFSO pulse is generated each time a new output is ready from DDC1. If the decimation rates of

DDC0 and DDC1 are identical, then it does not matter which DDC initiates the IF_DFSO pulse. If the decimation

rates are different, then the DDC with the smaller decimation ratio (higher output rate) should be chosen to

generate the IF_DFSO pulse. Note that in this case, outputs from the slower DDC are repeated for multiple

frames and it is the responsibility of the DSP software to compensate. This compensation is easiest to do if the

higher decimation rate is an integer multiple of the lower decimation rate.

Finally, if_dfso_mode is used to select alternate forms of frame sync. In the default case (if_dfso_mode = 0), the

frame sync is a high pulse one clock period wide that occurs the clock cycle before the first data bit of the serial

output. If if_dfso_mode is set to 1, then the frame sync changes polarity once per frame; again, one clock cycle

before the first data bit of the frame. If if_dfso_mode is set to 2, then the frame sync behaves like the default

frame sync except that the sync pulse is 16 clock periods wide. The three frame sync modes are illustrated in

Figure 15 and Figure 16. Table 8 shows the detailed timing conditions for Figure 16.

It is recommended that the DSP interface be configured to sample IF_DFSO and the four IF_DOUT lines on the

trailing edge of IF_DCLK. Table 9 shows the dout, if_dclk, if_dfso, and if_dout operation control settings.

Table 8. Detailed Timing Conditions

PARAMETER

MIN

TYP

MAX

UNIT

tD1

IF_DCLK0 to IF_DFS0 delay

-2.9

3.7

tD2

IF_DCLK0 to IF_DOUTx delay

-3.1

3.8

Table 9. Primary IF Control Register Settings

PARAMETER

ADDRESS

BITS

dout_en

if_dclk_div

4:0

if_dclk_edge

if_dfso_mode

8:7

if_dfso_select

if_dout0_config

15:0

if_dout1_config

15:0

if_dout2_config

15:0

if_dout3_config

15:0

Figure 15. Frame Sync Modes

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