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AFE8220TPZPQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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AFE8220TPZPQ1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 49 page ![]() I 2C BUS INTERFACE t HIGH t LOW t SU_DAT t HD_DAT t STOP t START SCK SDA V IL V IH t BUF I 2C Bus Interface Timing AFE8220-Q1 www.ti.com....................................................................................................................................................... SBAS455A – JANUARY 2009 – REVISED JULY 2009 Figure 3. I2C Bus Interface Timing PARAMETER MIN TYP MAX UNIT fSCK SCK clock frequency 0 400 kHz VIL Input voltage, low 0.3 × VDD V VIH Input voltage, high 0.7 × VDD V tSTART Setup time for START or repeated START condition 0.6 µs tSTOP Setup time for STOP condition 0.6 µs tLOW LOW period of SCK clock 1.3 µs tHIGH HIGH period of SCK clock 0.6 µs 100(1) tHD_DAT Data hold time from SCK falling ns 250 100(1) tSU_DAT Data setup time to SCK rising ns 250 tBUF Bus free time between a STOP and START condition 4.7 µs (1) Valid when MCLK > 20 MHz; otherwise is 250 ns. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): AFE8220-Q1 |
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