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AFE8220TPZPQ1 Datasheet(PDF) 10 Page - Texas Instruments |
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AFE8220TPZPQ1 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 49 page ![]() OUTPUT DATA INTERFACE DCLK DFSO DOUTx IA[15] IA[14] IA[13] IA[12] t D1 t D2 Output Data Interface Timing SPI CONTROL INTERFACE SCK CS MOSI MISO t L t SU3 t H3 t T t I t D4 SPI Control Interface Timing AFE8220-Q1 SBAS455A – JANUARY 2009 – REVISED JULY 2009....................................................................................................................................................... www.ti.com Figure 1. Output Data Interface Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tD1 DCLK to DFSO delay –2.9 3.7 ns tD2 DCLK to DOUTx delay –3.1 3.8 ns Figure 2. SPI Control Interface Timing PARAMETER CONDITIONS MIN TYP MAX UNIT fSCK Maximum SCK frequency 1 MHz tL CS lead time Trailing CS to leading SCK 5.0 ns tT CS trail time Trailing SCK to leading CS 5.0 ns tI CS idle time Leading CS to trailing CS 5.0 ns tSU3 MOSI to SCK setup time 5.0 ns tH3 MOSI to SCK hold time 1.0 ns tD4 SCK to MISO delay 1.0 10.4 ns 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): AFE8220-Q1 |
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