CY8C58LP datasheet(51/122 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 51 of 122

the multi sample mode, because the ADC is only reset once at

the end of conversion.

More information on output formats is provided in the Technical

Reference Manual.

8.2.3 Start of Conversion Input

The SoC signal is used to start an ADC conversion. A digital

clock or UDB output can be used to drive this input. It can be

used when the sampling period must be longer than the ADC

conversion time or when the ADC must be synchronized to other

hardware. This signal is optional and does not need to be

connected if ADC is running in a continuous mode.

8.2.4 End of Conversion Output

The EoC signal goes high at the end of each ADC conversion.

This signal may be used to trigger either an interrupt or DMA

request.

8.3 Successive Approximation ADC

The CY8C58LP family of devices has two Successive

Approximation (SAR) ADCs. These ADCs are 12-bit at up to 1

Msps, with single-ended or differential inputs, making them

useful for a wide variety of sampling and control applications.

8.3.1 Functional Description

In a SAR ADC an analog input signal is sampled and compared

with the output of a DAC. A binary search algorithm is applied to

the DAC and used to determine the output bits in succession

from MSB to LSB. A block diagram of one SAR ADC is shown in

Figure 8-5.

Figure 8-5. SAR ADC Block Diagram

The input is connected to the analog globals and muxes. The

frequency of the clock is 18 times the sample rate; the clock rate

ranges from 1 to 18 MHz.

8.3.2 Conversion Signals

Writing a start bit or assertion of a start of frame (SOF) signal is

used to start a conversion. SOF can be used in applications

where the sampling period is longer than the conversion time, or

when the ADC needs to be synchronized to other hardware. This

signal is optional and does not need to be connected if the SAR

ADC is running in a continuous mode. A digital clock or UDB

output can be used to drive this input. When the SAR is first

powered up or awakened from any of the sleeping modes, there

is a power up wait time of 10 µs before it is ready to start the first

conversion.

When the conversion is complete, a status bit is set and the

output signal end of frame (EOF) asserts and remains asserted

until the value is read by either the DMA controller or the CPU.

The EOF signal may be used to trigger an interrupt or a DMA

request.

8.3.3 Operational Modes

A ONE_SHOT control bit is used to set the SAR ADC conversion

mode to either continuous or one conversion per SOF signal.

DMA transfer of continuous samples, without CPU intervention,

is supported.

8.4 Comparators

The CY8C58LP family of devices contains four comparators.

Comparators have these features:

■ Input offset factory trimmed to less than 5 mV

■ Rail-to-rail common mode input range (VSSA to VDDA)

■ Speed and power can be traded off by using one of three

modes: fast, slow, or ultra low power

■ Comparator outputs can be routed to look up tables to perform

simple logic functions and then can also be routed to digital

blocks

■ The positive input of the comparators may be optionally passed

through a low pass filter. Two filters are provided

■ Comparator inputs can be connections to GPIO, DAC outputs

and SC block outputs

8.4.1 Input and Output Interface

The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus

and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The

output of that LUT is routed to the UDB DSI.

S/H

DAC

array

vin

vrefp

vrefn

comparator

SAR

digital

D0:D11

clock

autozero

reset

clock

power

filtering

POWER

GROUND

vrefp

vrefn

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