CY8C58LP datasheet(29/122 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 29 of 122

services and to reduce wakeup time. At these times the PRES

circuit is also buzzed to allow periodic voltage monitoring.

After PRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

■ ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog

High Voltage Interrupt

Interrupt circuits are available to detect when VDDA and

VDDD go outside a voltage range. For AHVI, VDDA is

compared to a fixed trip level. For ALVI and DLVI, VDDA and

VDDD are compared to trip levels that are programmable, as

listed in Table 6-5. ALVI and DLVI can also be configured to

generate a device reset instead of an interrupt.

The monitors are disabled until after IPOR. During sleep mode

these circuits are periodically activated (buzzed). If an interrupt

occurs during buzzing then the system first enters its wakeup

sequence. The interrupt is then recognized and may be

serviced.

The buzz frequency is adjustable, and should be set to be less

than the minimum time that any voltage is expected to be out

of range. For details on how to adjust the buzz frequency, see

the TRM.

6.3.1.2

Other Reset Sources

■ XRES - External Reset

PSoC 5LP has either a single GPIO pin that is configured as

an external reset or a dedicated XRES pin. Either the

dedicated XRES pin or the GPIO pin, if configured, holds the

part in reset while held active (low). The response to an XRES

is the same as to an IPOR reset. The external reset is active

low. It includes an internal pull-up resistor. XRES is active

during sleep and hibernate modes.

After XRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

■ SRES - Software Reset

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

Another register bit exists to disable this function.

■ WRES - Watchdog Timer Reset

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

Note

IPOR disables the watchdog function. The program must

enable the watchdog function at an appropriate point in the

code by setting a register bit. When this bit is set, it cannot be

cleared again except by an IPOR power on reset event.

6.4 I/O System and Routing

PSoC I/Os are extremely flexible. Every GPIO has analog and

digital I/O capability. All I/Os have a large number of drive modes,

which are set at POR. PSoC also provides up to four individual

I/O voltage domains through the VDDIO pins.

There are two types of I/O pins on every device; those with USB

provide a third type. Both general purpose I/O (GPIO) and

special I/O (SIO) provide similar digital functionality. The primary

differences are their analog capability and drive strength.

Devices that include USB also provide two USBIO pins that

support specific USB functionality as well as limited GPIO

capability.

All I/O pins are available for use as digital inputs and outputs for

both the CPU and digital peripherals. In addition, all I/O pins can

generate an interrupt. The flexible and advanced capabilities of

the PSoC I/O, combined with any signal to any pin routability,

greatly simplify circuit design and board layout. All GPIO pins can

be used for analog input, CapSense[9], and LCD segment drive,

while SIO pins are used for voltages in excess of VDDA and for

programmable output voltages.

■ Features supported by both GPIO and SIO:

❐ User programmable port reset state

❐ Separate I/O supplies and voltages for up to four groups of I/O

❐ Digital peripherals use DSI to connect the pins

❐ Input or output or both for CPU and DMA

❐ Eight drive modes

❐ Every pin can be an interrupt source configured as rising

edge, falling edge or both edges. If required, level sensitive

interrupts are supported through the DSI

❐ Dedicated port interrupt vector for each port

❐ Slew rate controlled digital output drive mode

❐ Access port control and configuration registers on either port

basis or pin basis

❐ Separate port read (PS) and write (DR) data registers to avoid

read modify write errors

❐ Special functionality on a pin by pin basis

■ Additional features only provided on the GPIO pins:

❐ LCD segment drive on LCD equipped devices

❐ CapSense[9]

❐ Analog input and output capability

❐ Continuous 100 µA clamp current capability

❐ Standard drive strength down to 1.71 V

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Interrupt

Supply

Normal Voltage

Range

Available Trip

Settings

DLVI

VDDD

1.71 V-5.5 V

1.70 V-5.45 V in

250 mV increments

ALVI

VDDA

1.71 V-5.5 V

1.70 V-5.45 V in

250 mV increments

AHVI

VDDA

1.71 V-5.5 V

5.75 V

Note

9. GPIOs with opamp outputs are not recommended for use with CapSense.

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