CY8C58LP datasheet(65/122 Pages) CYPRESS

65 / 122 page

PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 65 of 122

Figure 11-1. IDD vs Frequency at 25 °C

11.3 Power Regulators

Specifications are valid for –40 °C

≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.3.1 Digital Core Regulator

Table 11-4. Digital Core Regulator DC Specifications

Notes

22. Based on device characterization (not production tested). USBIO pins tied to ground (VSSD).

23. Based on device characterization (Not production tested).

Table 11-3. AC Specifications[23]

Parameter

Description

Conditions

Min

Typ

Max

Units

FCPU

CPU frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

67.01

MHz

FBUSCLK

Bus frequency

1.71 V

≤ VDDD ≤ 5.5 V

–

67.01

MHz

Svdd

VDD ramp rate

–

0.066

V/µs

TIO_INIT

Time from VDDD/VDDA/VCCD/VCCA ≥ IPOR to

I/O ports set to their reset states

–

µs

TSTARTUP

Time from VDDD/VDDA/VCCD/VCCA ≥ PRES

to CPU executing code at reset vector

VCCA/VDDA = regulated from

VDDA/VDDD, no PLL used, fast IMO

boot mode (48 MHz typ.)

–

µs

VCCA/VCCD = regulated from

VDDA/VDDD, no PLL used, slow IMO

boot mode (12 MHz typ.)

–

µs

TSLEEP

Wakeup from sleep mode –

Application of non-LVD interrupt to beginning

of execution of next CPU instruction

–

µs

THIBERNATE Wakeup from hibernate mode – Application

of external interrupt to beginning of

execution of next CPU instruction

–

125

µs

Parameter

Description

Conditions

Min

Typ

Max

Units

VDDD

Input voltage

1.8

–

5.5

VCCD

Output voltage

–

1.80

–

Regulator output capacitor

±10%, X5R ceramic or better. The two VCCD

pins must be shorted together, with as short

a trace as possible, see “Power System”

section on page 24

–1

–

µF

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