CY8C58LP datasheet(99/122 Pages) CYPRESS

99 / 122 page

PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 99 of 122

Figure 11-68. Bandwidth vs. Temperature, at Different Gain

Settings, Power Mode = High

Figure 11-69. Noise vs. Frequency, Vdda = 5 V,

Power Mode = High

11.5.12 Temperature Sensor

11.5.13 LCD Direct Drive

Note

64. Based on device characterization (Not production tested).

Table 11-43. PGA AC Specifications[64]

Parameter

Description

Conditions

Min

Typ

Max

Units

BW1

–3 dB bandwidth

Power mode = high,

gain = 1, input = 100 mV

peak-to-peak

6.7

–

MHz

SR1

Slew rate

Power mode = high,

gain = 1, 20% to 80%

3––

V/µs

Input noise density

Power mode = high,

Vdda = 5 V, at 100 kHz

–43

–

nV/sqrtHz

0.1

-40

-20

20406080

Temperature, °C

Gain = 1

Gain = 24

Gain = 48

100

1000

0.01

0.1

100

1000

Frequency, kHz

Table 11-44. Temperature Sensor Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Temp sensor accuracy

Range: –40 °C to +85 °C

–

±5

–

°C

Table 11-43. LCD Direct Drive DC Specifications[64]

Parameter

Description

Conditions

Min

Typ

Max

Units

ICC

LCD Block (no glass)

Device sleep mode with wakeup at

400Hz rate to refresh LCD, bus, clock =

3MHz, Vddio = Vdda = 3V, 8 commons,

16 segments, 1/5 duty cycle, 40 Hz

frame rate, no glass connected

–81

–

μA

ICC_SEG

Current per segment driver

Strong drive mode

–

260

–

µA

VBIAS

LCD bias range (VBIAS refers to the

main output voltage(V0) of LCD DAC)

VDDA ≥ 3 V and VDDA ≥ VBIAS

2–

LCD bias step size

VDDA ≥ 3 V and VDDA ≥ VBIAS

–

9.1 × VDDA

–mV

LCD capacitance per segment/

common driver

Drivers may be combined

–

500

5000

Maximum segment DC offset

VDDA ≥ 3 V and VDDA ≥ VBIAS

––

IOUT

Output drive current per segment

driver)

VDDIO = 5.5 V, strong drive mode

355

–

710

µA

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