CY8C58LP datasheet(103/122 Pages) CYPRESS

103 / 122 page

PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 103 of 122

11.6.7 USB

11.6.8 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Note

68. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications[37] on page 76.

Table 11-59. USB DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

VUSB_5

Device supply for USB operation

USB configured, USB regulator

enabled

4.35

–

5.25

VUSB_3.3

USB configured, USB regulator

bypassed

3.15

–

3.6

VUSB_3

USB configured, USB regulator

bypassed[68]

2.85

–

3.6

IUSB_Configured Device supply current in device active

mode, bus clock and IMO = 24 MHz

VDDD = 5 V, FCPU = 1.5 MHz

–

VDDD = 3.3 V, FCPU = 1.5 MHz

–

IUSB_Suspended Device supply current in device sleep

mode

VDDD = 5 V, connected to USB

host, PICU configured to wake on

USB resume signal

–0.5

–

VDDD = 5 V, disconnected from

USB host

–0.3

–

VDDD = 3.3 V, connected to USB

host, PICU configured to wake on

USB resume signal

–0.5

–

VDDD = 3.3 V, disconnected from

USB host

–0.3

–

Table 11-60. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

FMAX_TIMER Maximum frequency of 16-bit timer in

a UDB pair

–

67.01

MHz

FMAX_ADDER Maximum frequency of 16-bit adder in

a UDB pair

–

67.01

MHz

FMAX_CRC

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

–

67.01

MHz

PLD Performance

FMAX_PLD

Maximum frequency of a two-pass

PLD function in a UDB pair

–

67.01

MHz

Clock to Output Performance

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-70.

25 °C, Vddd

≥ 2.7 V

–

tCLK_OUT

Propagation delay for clock in to data

out, see Figure 11-70.

Worst-case placement, routing,

and pin selection

–

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