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CY8C58LP Datasheet(PDF) 86 Page - Cypress Semiconductor |
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CY8C58LP Datasheet(HTML) 86 Page - Cypress Semiconductor |
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86 / 122 page  PRELIMINARY PSoC® 5LP: CY8C58LP Family Datasheet Document Number: 001-84932 Rev. ** Page 86 of 122 Figure 11-37. SAR ADC IDD vs sps, VDDA = 5 V, Continuous Sample Mode, External Reference Mode Figure 11-38. SAR ADC Noise Histogram, 1000 samples, 700 ksps, Internal Reference No Bypass, VIN = VREF/2 Figure 11-39. SAR ADC Noise Histogram, 1000 samples, 700 ksps, Internal Reference Bypassed, VIN = VREF/2 Note 47. Based on device characterization (Not production tested). Table 11-29. SAR ADC AC Specifications[48] Parameter Description Conditions Min Typ Max Units Fclk SAR clock frequency 1 – 18 MHz Tc Conversion time One conversion requires 18 SAR clocks. Maximum sample rate is 1 Msps 1 – 18 µs Startup time – – 10 µs SINAD Signal-to-noise ratio 68 – – dB THD Total harmonic distortion – – 0.02 % |
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